High-performance analog-to-digital converters (ADCs) employ input buffers to present a high impedance input isolated from the switching transients in the ADC front end. Time-interleaved ADCs continue to push ADC bandwidth and linearity higher. As a result, the bandwidth and linearity requirements of the input buffer are pushed higher in order to not limit the ADC performance. Source follower buffers of various configurations can be employed for buffer function. Feedback loops can be employed to enhance the low frequency linearity. The problem with this approach is the high-frequency linearity becomes compromised as the limits of the feedback loop are approached. It is desirable to provide an input buffer that maintains linearity at both high and low frequencies.